library verilog;
use verilog.vl_types.all;
entity dbg_register is
    generic(
        WIDTH           : integer := 8
    );
    port(
        DataIn          : in     vl_logic_vector;
        DataOut         : out    vl_logic_vector;
        Write           : in     vl_logic;
        Clk             : in     vl_logic;
        Reset           : in     vl_logic;
        Default         : in     vl_logic_vector
    );
end dbg_register;
